The present invention relates generally to integrated circuits (ICs) and more particularly, to duty cycle correction of a clock signal.
Integrated circuits (ICs) include multiple clock domains. A clock domain is characterized by being driven by a clock signal. The clock signal may be generated within the IC or provided from a clock source external to the IC. Each clock domain contains logic elements such as flip-flops and latches, which operate upon the receipt of active edges of the clock signal.
The clock signal is generated using circuits such as Phase Locked Loops (PLLs) and oscillators. The clock signal is subsequently routed to the various clock domains. Often the clock sources are located far from the site where the clock signals are required. Thus, the clock signal may have to pass through several buffer stages before reaching the core logic circuit. As a result, the clock signal may become distorted, leading to a change in the duty cycle of the clock signal, which may lead to degradation in the performance of the IC.
Various circuits have been designed to correct the duty cycle of the clock signal received by the core logic circuits. FIG. 1 illustrates an example of a conventional duty cycle correction circuit 100. The duty cycle correction circuit 100 includes a PLL clock generator 102, a buffer chain 104, a resistor ladder 106, a comparator 108, a duty cycle-to-voltage converter 110, a voltage-to-duty cycle converter 112, and an output buffer 114. The voltage-to-duty cycle converter 112 includes a current starved inverter 116, and current sources 118a and 118b. 
The PLL clock generator 102 generates a clock signal of a predefined frequency and duty cycle. The clock signal passes through the buffer chain 104, which is representative of a clock path that the clock signal traverses before reaching the clock domains or the core logic circuit. Due to passage through the buffer chain 104, the emerging clock signal has a distorted duty cycle. The clock signal with distorted duty cycle is provided to the voltage-to-duty cycle converter 112. The current starved inverter 116 adjusts the duty cycle of the clock signal as a function of the magnitude of current generated by the current sources 118a and 118b. The current generated by the current sources 118a and 118b adjusts, i.e., increases or decreases, the rise and fall times of the clock signal. The current source 118a is a p-type metal oxide semiconductor (PMOS) transistor and the current source 118b is an n-type metal oxide semiconductor (NMOS) transistor.
The magnitude of the current generated by the current sources 118a and 118b is a function of a control signal output by the comparator 108, which represents the difference (error) existing between input signals provided at positive and negative terminals of the comparator 108. The input signal at the negative terminal of the comparator 108 is obtained from the duty cycle-to-voltage converter 110. The duty cycle-to-voltage converter 110 is an RC circuit that receives the distorted duty cycle clock signal from the output buffer 114. The duty cycle-to-voltage converter 110 generates an output signal having a voltage magnitude that represents the duty cycle of the clock signal. The output signal may be referred to as a distorted duty cycle signal. This distorted duty cycle signal is provided to the negative terminal of the comparator 108.
The input signal provided at the positive terminal of the comparator 108 is a reference voltage (Vref). If the ideal duty cycle of the clock signal is 50% and the voltage magnitude of the clock signal when it is high is Vdd, the voltage signal representing this clock signal with ideal duty cycle would be Vdd/2. Therefore, Vref is obtained by coupling the positive terminal of the comparator 108 to a midpoint of the resistor ladder 106. Thus, Vref=Vdd/2.
The comparator 108 compares the output of the duty cycle-to-voltage converter 110 (magnitude of which is either <Vdd/2 or >Vdd/2) with the reference voltage signal (magnitude=Vdd/2) to obtain an error signal. The greater the difference between the two input signals, the greater the magnitude of the error signal.
As explained earlier, the error signal is used to control the magnitude of the current generated by the current sources 118a and 118b. The current generated by the current sources 118a and 118b in turn controls the magnitude of adjustment provided to the distorted duty cycle clock signal by the current starved inverter 116. The adjustment provided to the distorted duty cycle clock signal shifts the duty cycle closer to the ideal duty cycle. The adjustment is provided to an incoming clock signal, i.e., output of the buffer chain 104, until the duty cycle of the output clock signal, i.e., output of the output buffer 114, is equal to the ideal duty cycle. In a steady state, the reference signal provided to the positive terminal of the comparator 108 becomes equal to the output of the duty cycle-to-voltage converter 110 provided to the negative terminal of the comparator 108. The duty cycle correction circuit 100 thus provides a corrected duty cycle clock signal.
However, the duty cycle correction circuit 100 requires a reference signal for comparison with the distorted duty cycle clock signal. The reference signal is generated using the resistor ladder 106. Further, the comparator 108, which is an operational amplifier, requires a supply voltage higher than the supply voltage of the logic circuit to which the corrected clock signal is provided. Additionally, the comparator 108 requires a current reference circuit in order to function correctly. It would be advantageous to have a duty cycle correction circuit that consumed less power. It also would be advantageous to have a duty cycle correction circuit that operated at the same voltage as the circuits to which the clock signal is provided.